Research

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Our research group develops advanced wafer‑level technologies to address the fundamental contamination and reliability challenges that limit the performance of next‑generation 3D‑stacked CMOS image sensors. To overcome the shortcomings of conventional intrinsic gettering (IG) and to meet the requirements of low‑thermal‑budget device fabrication, we pursue a comprehensive approach that integrates ion implantation, annealing science, wafer bonding, and impurity characterization.
 

1. Silicon Wafer Gettering Design Using Multi‑Element Molecular Ion Implantation

A central focus of our work is the design of high‑gettering‑capability silicon wafers using multi‑element molecular ion implantation. By introducing molecular species with tailored chemical reactivity, we aim to create efficient gettering sites that suppress metallic impurity contamination during device processing. This concept forms the foundation for enabling reliable 3D‑stacked backside‑illuminated CMOS image sensor fabrication.

 

2. Ultra‑High‑Dose Molecular Ion Implantation and Advanced Annealing Techniques

Building on this foundation, we develop ultra‑high‑dose molecular ion implanted wafers combined with low‑temperature annealing techniques, including variable‑frequency microwave annealing and ultra‑fast pulsed‑laser annealing. These methods promote defect recovery and impurity trapping under short‑duration thermal conditions, making them highly compatible with modern device integration schemes.

 

3. Gettering‑Enhanced Wafer Bonding Using Cluster‑Enhanced Surface Activation

To further enhance contamination control during 3D integration, we investigate cluster‑enhanced surface activation bonding. This technique improves wafer‑to‑wafer bonding strength while simultaneously providing gettering functionality at the bonding interface, reducing defect formation in stacked structures.

 

4. Copper/Ruthenium Thin‑Film Surface Chemistry in TSV Processes

Our research also extends to Cu/Ru thin‑film surface chemistry in TSV processes, where we analyze interfacial reactions using in‑situ multi‑internal‑reflection FTIR under ultra‑high vacuum. These insights help address copper diffusion issues in hybrid‑bonded architectures.

 

5. High‑Sensitivity Impurity Detection in CMOS Devices

Finally, we develop high‑sensitivity impurity detection methodologies, including DLTS, EBIC, and TDTS, to evaluate the impact of trace metallic contaminants on device performance. These analytical tools are essential for validating gettering effectiveness and ensuring the reliability of advanced CMOS imaging devices.

 

6. Development of Gettering Technologies for Silicon Interposer Materials

In parallel, we explore getter‑enhanced silicon interposer technologies using pulsed‑laser annealing and high‑current ion implantation. These approaches support contamination control in heterogeneous integration platforms beyond CMOS image sensors.

Together, these research activities form an integrated technological framework that supports the development of robust, contamination‑resistant silicon wafers for future 3D‑stacked semiconductor devices.