Background
Modern CMOS image sensors are essential components in consumer electronics, powering high‑performance cameras in smartphones, tablets, and various imaging systems. As market demand continues to grow for higher sensitivity, improved noise performance, and faster data processing, the development of advanced device structures—particularly 3D‑stacked backside‑illuminated CMOS image sensors—has become increasingly important.
However, several critical technological challenges still hinder device performance and reliability. Among these, metallic impurity contamination during thermal and plasma‑based processes remains one of the most serious issues. Such impurities degrade key device characteristics, including photodiode junction leakage current, gate oxide breakdown voltage, and minority carrier recombination lifetimes. In addition, copper diffusion in through‑silicon‑via (TSV) structures poses significant reliability concerns for 3D‑stacked architectures.
Conventional intrinsic gettering (IG) techniques are no longer sufficient for modern CMOS fabrication, where low thermal budgets and complex 3D integration schemes limit the applicability of traditional high‑temperature processes. These limitations necessitate the exploration of alternative gettering strategies that are compatible with advanced device manufacturing.
Our research group addresses these challenges by developing innovative wafer‑level gettering and contamination‑control technologies, including molecular and cluster ion implantation, low‑temperature annealing methods such as microwave and pulsed‑laser annealing, and advanced bonding techniques. Through these efforts, we aim to establish a robust technological foundation for next‑generation 3D‑stacked CMOS image sensors.
However, several critical technological challenges still hinder device performance and reliability. Among these, metallic impurity contamination during thermal and plasma‑based processes remains one of the most serious issues. Such impurities degrade key device characteristics, including photodiode junction leakage current, gate oxide breakdown voltage, and minority carrier recombination lifetimes. In addition, copper diffusion in through‑silicon‑via (TSV) structures poses significant reliability concerns for 3D‑stacked architectures.
Conventional intrinsic gettering (IG) techniques are no longer sufficient for modern CMOS fabrication, where low thermal budgets and complex 3D integration schemes limit the applicability of traditional high‑temperature processes. These limitations necessitate the exploration of alternative gettering strategies that are compatible with advanced device manufacturing.
Our research group addresses these challenges by developing innovative wafer‑level gettering and contamination‑control technologies, including molecular and cluster ion implantation, low‑temperature annealing methods such as microwave and pulsed‑laser annealing, and advanced bonding techniques. Through these efforts, we aim to establish a robust technological foundation for next‑generation 3D‑stacked CMOS image sensors.